View KA555IDTF_7318918.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?2002 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.2 features ? high current drive capability (200ma) ? adjustable duty cycle ? temperature stability of 0.005%/ c ? timing from msec to hours ? turn off time less than 2msec applications ? precision timing ? pulse generation ? time delay generation ? sequential timing description the ka555 is a highly stable controller capable of producing accurate timing pulses. with monos table operation, the time delay is controlled by one external resistor and one capacitor. with astable operation, the frequency and duty cycle are accurately controlled with two external resistors and one capacitor. 8-dip 8-sop 1 1 internal block diagram f/f output stage 1 7 5 2 3 4 6 8 rrr comp. comp. discharging tr. vref vcc discharge threshold control voltage gnd trigger output reset ka555 single timer
ka555 2 absolute maximum ratings (t a = 25 c) parameter symbol value unit supply voltage v cc 16 v lead temperature (soldering 10sec) t lead 300 c power dissipation p d 600 mw operating temperature range ka555/ka555i t opr 0 ~ +70 / -40 ~ +85 c storage temperature range t stg - 65 ~ +150 c
ka555 3 electrical characteristics (t a = 25 c, v cc = 5 ~ 15v, unless otherwise specified) notes: 1. supply current when output is high is typically 1ma less at v cc = 5v 2. tested at v cc = 5.0v and v cc = 15v 3. this will determine maximum value of r a + r b for 15v operation, the max. total r = 20m ? , and for 5v operation the max. total r = 6.7m ? parameter symbol conditions min. typ. max. unit supply voltage v cc -4.5-16v supply current * 1 (low stable) i cc v cc = 5v, r l = -36 ma v cc = 15v, r l = -7.515 ma timing error * 2 (monos table) initial accuracy drift with temperature drift with supply voltage accur ? t/ ? t ? t/ ? v cc r a = 1k ? to100k ? c = 0.1 f -1.0 50 0.1 3.0 0.5 % ppm/ c %/v timing error * 2 (astable) initial accuracy drift with temperature drift with supply voltage accur ? t/ ? t ? t/ ? v cc r a = 1k ? to 100k ? c = 0.1 f - 2.25 150 0.3 -% ppm/ c %/v control voltage v cc v cc = 15v 9.0 10.0 11.0 v v cc = 5v 2.6 3.33 4.0 v threshold voltage v th v cc = 15 v - 10.0 - v v cc = 5v - 3.33 - v threshold current * 3 i th - - 0.1 0.25 a trigger voltage v tr v cc = 5v 1.1 1.67 2.2 v v cc = 15v 4.5 5 5.6 v trigger current i tr v tr = 0v 0.01 2.0 a reset voltage v rst - 0.4 0.7 1.0 v reset current i rst - 0.1 0.4 ma low output voltage v ol v cc = 15v i sink = 10ma i sink = 50ma -0.06 0.3 0.25 0.75 v v v cc = 5v i sink = 5ma - 0.05 0.35 v high output voltage v oh v cc = 15v i source = 200ma i source = 100ma 12.75 12.5 13.3 -v v v cc = 5v i source = 100ma 2.75 3.3 - v rise time of output t r - - 100 - ns fall time of output t f - - 100 - ns discharge leakage current i lkg - - 20 100 na
ka555 4 application information table1 below is the basic operating table of 555 timer: when the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. only when the high signal is applied to the reset terminal, timer's output changes according to threshold voltage and trigger voltage. when the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge tr. turns on, lowering the threshold voltage to below 1/3 of the supply voltage. during this time, the timer output is maintained low. later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's inter nal discharge tr. turns off, increasing the threshold voltage and driving the timer output again at high . 1. monos table operation table 1. basic operating table threshold voltage (v th )(pin6) trigger voltage (v tr )(pin2) reset(pin4) output(pin3) discharging tr. (pin7) don't care don't care low low on v th > 2vcc / 3 v th > 2vcc / 3 high low on vcc / 3 < v th < 2 vcc / 3 vcc / 3 < v th < 2 vcc / 3 high - - v th < vcc / 3 v th < vcc / 3 high high off 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 -3 10 -2 10 -1 10 0 10 1 10 2 10m ? ? ? ? 1m ? ? ? ? 10k ? ? ? ? 100k ? ? ? ? r a =1k ? ? ? ? capacitance(uf) time delay(s) figure 1. monoatable circuit figure 2. resistance and capacitance vs. time delay(t d ) figure 3. waveforms of monostable operation 1 5 6 7 8 4 2 3 reset vcc disch thres cont gnd out trig +vcc r a c1 c2 r l trigger
ka555 5 figure 1 illustrates a monos table circuit. in this mode, the timer generates a fixed pulse whenever the trigger voltage falls below vcc/3. when the trigger pulse voltage applied to the #2 pin falls below vcc/3 while the timer output is low, the timer's internal flip-flop turns the discharging tr. off and causes the timer output to become high by charging the external capacitor c1and setting the flip-flop output at the same time. the voltage across the external capacitor c1, v c1 increases exponentially with the time constant t=r a *c and reaches 2vcc/3 at td=1.1r a *c. hence, capacitor c1 is charged through resistor r a . the greater the time constant r a c, the longer it takes for the v c1 to reach 2vcc/3. in other words, the time constant r a c controls the output pulse width. when the applied voltage to the capacitor c1 reaches 2vcc/3, the comparator on the trigger terminal resets the flip-flop, turning the discharging tr. on. at this time, c1 begins to discharge and the timer output converts to low. in this way, the timer operating in monos table repeats the above process. figure 2 shows the time constant relationship based on r a and c. figure 3 shows the general waveforms during monos table operation. it must be noted that, for normal operation, the trigger pulse voltage needs to maintain a minimum of vcc/3 before the timer output turns low. that is, although the output remains unaffected even if a different trigger pulse is applied while the outpu t is high, it may be affected and the waveform not operate properly if the trigger pulse voltage at the end of the output pulse remains at below vcc/3. figure 4 shows such timer output abnormality . 2. astable operation figure 4. waveforms of monos table operation (abnormal) 100m 1 10 100 1k 10k 100k 1e-3 0.01 0.1 1 10 100 10m ? ? ? ? 1m ? ? ? ? 100k ? ? ? ? 10k ? ? ? ? 1k ? ? ? ? (r a +2r b ) capacitance(uf) frequency(hz) figure 5. astable circuit figure 6. capacitance and resistance vs. frequency 1 5 6 7 8 4 2 3 reset vcc disch thres cont gnd out trig +vcc r a c1 c2 r l r b
ka555 6 an astable timer operation is achieved by adding resistor r b to figure 1 and configuring as shown on figure 5. in astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi vibrator. when the timer output is high, its internal discharging tr. turns off and the v c1 increases by exponential function with the time constant (r a +r b )*c. when the v c1 , or the threshold voltage, reaches 2vcc/3, the comparator output on the trigger terminal becomes high, resetting the f/f and causing the timer output to become low. this in turn turns on the discharging tr. and the c1 discharges through the discharging channel formed by r b and the discharging tr. when the v c1 falls below vcc/3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. the discharging tr. turns off and the v c1 rises again. in the above process, the section where the timer output is high is the time it takes for the v c1 to rise from vcc/3 to 2vcc/3, and the section where the timer output is low is the time it takes for the v c1 to drop from 2vcc/3 to vcc/3. when timer output is high, the equivalent circuit for charging capacitor c1 is as follows : since the duration of the timer output high state(t h ) is the amount of time it takes for the v c1 (t) to reach 2vcc/3, figure 7. waveforms of astable operation vcc r a r b c1 vc1 (0-)=vcc/ 3 c 1 dv c1 dt ? ? ? ? ? ? ? ? v cc v0- () ? r a r b + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 1 () v c1 0+ () v cc 3 ? = 2 () v c1 t () v cc 1 2 3 ? ? e - t r a r b + () c1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ?? ?? ? ?? ?? ?? ?? ?? = 3 ()
ka555 7 the equivalent circuit for discharging capacitor c1 when timer output is low as follows: since the duration of the timer output low state( t l ) is the amount of time it takes for the v c1 (t) to reach vcc/3, since r d is normally r b >> r d although related to the size of discharging tr., t l =0.693r b c 1 (10) consequently, if the timer operates in astable, the period is the same with 't=t h +t l =0.693(ra+r b )c 1 +0.693r b c 1 =0.693(r a +2r b )c 1 ' because the period is the sum of the charge time and discharge time. and since frequency is the reciprocal of the period, the following applies . 3. frequency divider by adjusting the length of the timing cycle, the basic circuit of figure 1 can be made to operate as a frequency divider. figur e 8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. v c1 t () 2 3 ? ? v cc v = cc 1 2 3 ? ? e - t h r a r b + () c1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ?? ?? ? ?? ?? ?? ?? ?? = 4 () t h c 1 r a r b + () in2 0.693 r a r b + () c 1 = = 5 () c1 r b r d v c1 (0-)=2vcc/3 c 1 dv c1 dt ? ? ? ? ? ? ? ? ? 1 r a r b + ? ? ? ? ? ? ? ? ? ? ? ? ? ? v c1 0 = + 6 () v c1 t () 2 3 ? ? v cc e - t r a r d + () c1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 7 () 1 3 ? ? v cc 2 3 ? ? v cc e - t l r a r d + () c1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 8 () t l c 1 r b r d + () in2 0.693 r b r d + () c 1 = = 9 () frequency, f 1 t ? ? 1.44 r a 2r b + () c 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? == 11 ()
ka555 8 4. pulse width modulation the timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the reference of the timer's internal comparators. figure 9. illustrates the pulse width modulation circuit. when the continuous trigger pulse train is applied in the monos table mode, the timer output width is modulated according to the signal applied to the control terminal. sine wave as well as other waveforms may be applied as a signal to the control terminal. figure 10 shows an example of pulse width modulation waveform. 5. pulse position modulation if the modulating signal is applied to the control terminal while the timer is connected for astable operation as in figure 11, the timer becomes a pulse position modulator. in the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the timer output according to the modulation signal applied to the control terminal. figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave shape could be used. figure 8. waveforms of frequency divider operation 8 4 7 1 2 3 5 6 cont gnd vcc disch thres reset trig out +vcc trigger r a c output input figure 9. circuit for pulse width modulation figure 10. waveforms of pulse width modulation
ka555 9 6. linear ramp when the pull-up resistor ra in the monos table circuit shown in figure 1 is replaced with constant current source, the v c1 increases linearly, generating a linear ramp. figure 13 shows the linear ramp generating circuit and figure 14 illustrates the generated linear ramp waveforms. in figure 13, current source is created by pnp transistor q1 and resistor r1, r2, and r e . for example, if vcc=15v, r e =20k ? , r1=5kw, r2=10k ? , and v be =0.7v, v e =0.7v+10v=10.7v ic=(15-10.7)/20k=0.215ma when the trigger is started in a timer configured as shown in figure 13, the current flowing to capacitor c1 becomes a constant current generated by pnp transistor and resistors. 8 4 7 1 2 3 5 6 cont gnd vcc disch thres reset trig out +vcc r a c r b modulation output figure 11. circuit for pulse position modulation figure 12. waveforms of pulse position modulation figure 13. circuit for linear ramp figure 14. waveforms of linear ramp 1 5 6 7 8 4 2 3 reset vcc disch thres cont gnd out trig +vcc c2 r1 r2 c1 q1 output r e i c v cc v e ? r e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 12 () here, v e is v e v be r 2 r 1 r 2 + ? ? ? ? ? ? ? ? ? ? ? ? ? v cc + = 13 ()
ka555 10 hence, the v c is a linear ramp function as shown in figure 14. the gradient s of the linear ramp function is defined as follows: here the vp-p is the peak-to-peak voltage. if the electric charge amount accumulated in the capacitor is divided by the capacitance, the v c comes out as follows: v=q/c (15) the above equation divided on both sides by t gives us and may be simplified into the following equation. s=i/c (17) in other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant current flowing through the capacitor. if the constant current flow through the capacitor is 0.215ma and the capacitance is 0.02uf, the gradient of the ramp function at both ends of the capacitor is s=0.215m/0.022u=9.77v/ms. s v pp ? t ? ? ? ? ? ? ? ? ? ? = 14 () v t ? ? qt ? c ? ? ? ? ? ? ? = 16 ()
ka555 11 mechanical dimensions package dimensions in millimeters 6.40 0.20 3.30 0.30 0.130 0.012 3.40 0.20 0.134 0.008 #1 #4 #5 #8 0.252 0.008 9.20 0.20 0.79 2.54 0.100 0.031 () 0.46 0.10 0.018 0.004 0.060 0.004 1.524 0.10 0.362 0.008 9.60 0.378 max 5.08 0.200 0.33 0.013 7.62 0~15 0.300 max min 0.25 +0.10 ?.05 0.010 +0.004 ?.002 8-dip
ka555 12 mechanical dimensions (continued) package dimensions in millimeters 4.92 0.20 0.194 0.008 0.41 0.10 0.016 0.004 1.27 0.050 5.72 0.225 1.55 0.20 0.061 0.008 0.1~0.25 0.004~0.001 6.00 0.30 0.236 0.012 3.95 0.20 0.156 0.008 0.50 0.20 0.020 0.008 5.13 0.202 max #1 #4 #5 0~8 #8 0.56 0.022 () 1.80 0.071 max0.10 max0.004 max min + 0.10 -0.05 0.15 + 0.004 -0.002 0.006 8-sop
ka555 13 ordering information product number package operating temperature ka555 8-dip 0 ~ +70 c ka555d 8-sop ka555i 8-dip -40 ~ +85 c ka555id 8-sop
ka555 7/16/02 0.0m 001 stock#dsxxxxxxxx ? 2002 fairchild semiconductor corporation life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
product folder - fairchild p/n ka555 - single timer fairchild semiconductor space space space search | parametric | cross reference space product folders and datasheets application notes space space space find products home >> find products >> space space space space products groups space analog and mixed signal discrete interface logic microcontrollers non-volatile memory optoelectronics markets and applications new products product selection and parametric search cross-reference search technical information buy products technical support my fairchild company ka555 single timer related links request samples dotted line how to order products dotted line product change notices (pcns) dotted line support dotted line distributor and field sales representatives dotted line quality and reliability dotted line design tools contents general description | features | applications | product status/pricing/packaging | application notes general description the ka555 is a highly stable controller capable of producing accurate timing pulses. with monostable operation, the time delay is controlled by one external resistor and one capacitor. with astable operation, the frequency and duty cycle are accurately controlled with two external resistors and one capacitor. back to top features l high current drive capability (200ma) l adjustable duty cycle l temperature stability of 0.005%/c l timing from msec to hours l turn off time less than 2msec back to top applications l precision timing l pulse generation l time delay generation l sequential timing back to top space datasheet download this datasheet pdf e-mail this datasheet [e- mail] this page print version file:///e|/new/html/ka555.html (1 of 2) [7/26/02 12:21:03 pm]
product folder - fairchild p/n ka555 - single timer product status/pricing/packaging product product status package type leads packing method ka555d full production soic 8 rail ka555i full production dip 8 rail KA555IDTF full production soic 8 tape reel ka555 full production dip 8 rail ka555id full production soic 8 rail ka555dtf full production soic 8 tape reel back to top application notes an-9006: an-9006 igbt application note for camera strobe (146 k) jul 19, 2002 back to top space space home | find products | technical information | buy products | support | company | contact us | site index | privacy policy ? copyright 2002 fairchild semiconductor space space file:///e|/new/html/ka555.html (2 of 2) [7/26/02 12:21:03 pm]

▲Up To Search▲

Price & Availability of KA555IDTF

	To Download KA555IDTF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .